# Digital Electronics Quiz Vol- 2

This is the Digital electronics quiz vol- 2 which is more advanced than Digital Electronics Quiz-1. This is a bit more advanced version of it. Enjoy the Quiz game there will be 50 questions.

1. The output of Up counters goes on increasing due to _____

2. _____ input in an S-R Flip-Flop resets the flip-flop to its original value with an output Q, that will be at Logic ‘0’ or ‘1’ depending upon the set/reset condition.

3. Schmitt trigger can be used as

4. A counter circuit is usually made up of _____

5. A modulus-10 counter must have _____

6. What amongst the following is faster in operation?

7. How is a J-K flip-flop made to toggle?

8. How many AND, OR and EXOR gates are required for the configuration of full adder?

9. In SR flip-flop, ‘S’ stands for:

10. Which sequential circuits are used for counting pulses?

11. The register is a type of ________

12. The SR flip-flop can be considered as a ___ memory

13. A register that is used to store binary information is called a ________.

14. Why do the D flip-flops are said to be as Data Flip-flops’?

15. In D flip-flop, if clock input is HIGH & D=1, then output is ______[quads id=1]

Hint 16. _____ input in an S-R Flip-Flop resets the flip-flop to its original value with an output Q, that will be at Logic ‘0’ or ‘1’ depending upon the set/reset condition.

17. On a master-slave flip-flop, when is the master enabled?

18. If A, B, and C are the inputs of a full adder then the sum is given by ______

19.  The D flip-flop has _______ input.

20. When the J and K inputs are low, the state of the outputs Q and Q’ are

21. A register can be defined as ______

22. UP-DOWN counter is a combination of _______

23. In FPGA, vertical and horizontal directions are separated by __________

24. D flip-flop can be made from a J-K flip flop by making

25. A feature that distinguishes the J-K flip-flop from the D flip-flop is the

26. A shift register is defined as ______

27. Why is the extent of propagation delay in synchronous counter much lesser than that of the asynchronous counter?

28. Total number of inputs in a half adder is _____

29. Which type of device FPGA are?

30. The inputs in the PLD is given through _______

31. In serial shifting method, data shifting occurs ______

32. How many types of registers available?

33. Define trigger pulse?

34. Set pin going high in SR flip flop causes the output to go to

35. The process to activate a Flip-Flop is______

36. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

37. JK flip flop has _____

38. lf,  A and B are the inputs of a half adder, the carry is given by

39. Three decade counter would have _______

40. If the number of states in a counter are 2n, then the value of ‘n’ is ______

41. The main difference between a register and a counter is ______

42. In D flip-flop, if clock input is LOW, the D input ______

43. In an UP-counter, each flip-flop is triggered by _______

44. Basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?

45. A PLA is similar to a ROM in concept except that ______

46. An S-R Flip-Flop has 2 inputs marked ______& ______ and two outputs __&__.

47. In DOWN-counter, each flip-flop is triggered by _______

48. Which flip flops serve to be the fundamental building blocks of counters?

49. In which operation carry is obtained?

50. In an S-R Flip-Flop, Q output is set to logic 1 by applying logic 0 to the _____.

Question 1 of 50