Digital Electronics Quiz Vol- 2(Advance Level)

This is the Digital electronics quiz vol- 2 which is more advanced than Digital Electronics Quiz-1. This is a bit more advanced version of it. Enjoy the Quiz game there will be 50 questions.

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1. Why do the D flip-flops are said to be as Data Flip-flops’?

Due to its capability to receive data from flip-flop

Due to its capability to store data in flip-flop

Due to its capability to transfer the data into flip-flop

Due to erasing the data from the flip-flop

2. In SR flip-flop, ‘S’ stands for:

Stable

Selective

Set

Systematic

3. In which operation carry is obtained?

Addition

Subtraction

Multiplication

Both addition and subtraction

4. The inputs in the PLD is given through _______

NAND

NOR

AND

5. How many types of registers available?

6. UP-DOWN counter is a combination of _______

Latches

Flip-flops

UP counter

Up counter & down counter

7. The D flip-flop has _______ input.

8. An S-R Flip-Flop has 2 inputs marked ______& ______ and two outputs __&__.

Stable&Reset, Q & Q’

Select&Reset, Q’ & Q’

Set & Reset, Q& Q’

System&Reset, Q & Q’

9. JK flip flop has _____

No memory

Temporary memory

True Memory

Random

10. On a master-slave flip-flop, when is the master enabled?

when the gate is LOW

when the gate is HIGH

Can be either and or

None of the above

11. In serial shifting method, data shifting occurs ______

One bit at a time

simultaneously

Four bit at a time

Two bit at a time

12. The register is a type of ________

Combinational Circuit

Sequential Circuit

Latch

Counter

13. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

CLK = NGT, D = 0

CLK = PGT, D = 0

CLOCK NGT, D =1

CLOCK PGT, D =1

14. _____ input in an S-R Flip-Flop resets the flip-flop to its original value with an output Q, that will be at Logic ‘0’ or ‘1’ depending upon the set/reset condition.

Reset

Set

Clock

Q’

15. Set pin going high in SR flip flop causes the output to go to

Invalid

Default

16. In FPGA, vertical and horizontal directions are separated by __________

A line

A strobe

A channel

A flip-flop

17. In an S-R Flip-Flop, Q output is set to logic 1 by applying logic 0 to the _____.

S input

R input

Toggle input

CLK input

18. A counter circuit is usually made up of _____

A number of latches connected in cascade form

A number of NAND gates connected in cascade form

A number of NOR gates connected in cascade form

A number of flip-flops connected in cascade

19. If the number of states in a counter are 2ⁿ, then the value of ‘n’ is ______

Less than the number of flip flops

Greater than the number of flip flops

Equal to the number of flip flops

Unpredictable

20. Basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?

XOR or XNOR gates

AND or OR gates

NOR or NAND gates

AND or NOR gates

21. In an UP-counter, each flip-flop is triggered by _______

The output of the next flip-flop

The normal output of the preceding flip-flop

The inverted output of the preceding flip-flop

The clock pulse of the previous flip-flop

22. A shift register is defined as ______

The register capable of shifting information either to the right or to the left

The register capable of shifting information to another register

The register capable of shifting information to the right only

The register capable of shifting information to the left only

23. The SR flip-flop can be considered as a ___ memory

2-Bit

1-bit

8-Bit

4-Bit

24. A register can be defined as ______

The group of latches for storing one bit of information.

The group of latches for storing n-bit of information.

The group of flip-flops suitable for storing one bit of information.

The group of flip-flops suitable for storing binary information

25. How is a J-K flip-flop made to toggle?

J = 0, K = 0

J = 0, K = 1

J = 1, K = 0

J = 1, K = 1

26. _____ input in an S-R Flip-Flop resets the flip-flop to its original value with an output Q, that will be at Logic ‘0’ or ‘1’ depending upon the set/reset condition.

Reset

Set

Clock

Q’

27. Which sequential circuits are used for counting pulses?

Counters

Registers

Latches

Flip-Flops

28. How many AND, OR and EXOR gates are required for the configuration of full adder?

1, 2, 2

2, 1, 2

3, 1, 2

4, 0, 1

29. Total number of inputs in a half adder is _____

30. A modulus-10 counter must have _____

10 flip-flops

4 Flip-flops

2 flip-flops

Synchronous clocking

31. The main difference between a register and a counter is ______

A counter has no specific sequence of states

A register has no specific sequence of states

A register has the capability to store one bit of information but the counter has n-bit

A register counts data

32. A register that is used to store binary information is called a ________.

Binary Register

Data Register

Shift Register

Counter

33. Define trigger pulse?

A pulse that reverses the cycle of operation

A pulse that starts a cycle of operation

A pulse that prevents a cycle of operation

A pulse that enhances a cycle of operation

34. lf, A and B are the inputs of a half adder, the carry is given by

A AND B

A OR B

A X-OR B

A X-NOR B

35. In D flip-flop, if clock input is LOW, the D input ______

Has no effect

Goes high

Goes low

keeps deflecting

36. A feature that distinguishes the J-K flip-flop from the D flip-flop is the

toggle condition

preset input

clear input

type of clock

37. What amongst the following is faster in operation?

Sequential Circuits

Latches

Flip-flops

Combinational Circuits

38. Schmitt trigger can be used as

Squarewave generator

Comparator

Both A and B

None of the above

39. Three decade counter would have _______

2 BCD counters

3 BCD counters

4 BCD counters

5 BCD counters

40. The process to activate a Flip-Flop is______

Negative edge trigger

Positive edge trigger

Either positive or Negative edge trigger

Sinusoidal trigger

41. D flip-flop can be made from a J-K flip flop by making

J=K

J=K=1

J=Q, K=1

42. Which flip flops serve to be the fundamental building blocks of counters?

D Flip-Flop

T Flip-Flop

S-R Flip-Flop

J-K Flip-Flop

43. In DOWN-counter, each flip-flop is triggered by _______

The output of the next flip-flop

The normal output of the preceding flip-flop

The clock pulse of the previous flip-flop

The inverted output of the preceding flip-flop

44. The output of Up counters goes on increasing due to _____

Transmission of clock pulses

Reception of clock pulses

Both a and b

None of the above.

45. Why is the extent of propagation delay in synchronous counter much lesser than that of the asynchronous counter?

Due to the clocking of all flip flops at the same instant

Due to the increase in the number of states

Due to absence of mode control operation

Due to the absence of connection between the output of the preceding flip flop and the clock of the next one

46. When the J and K inputs are low, the state of the outputs Q and Q’ are

unchanged on clocking

changed on clocking

changed on output

changed on input

47. In D flip-flop, if clock input is HIGH & D=1, then output is ______[quads id=1]

Hint

Toggle

Invaid

48. A PLA is similar to a ROM in concept except that ______

It hasn’t capability to read only

It hasn’t capability to read or write operation

It hasn’t capability to write only

t doesn’t provide full decoding to the variables

49. If A, B, and C are the inputs of a full adder then the sum is given by ______

A AND B AND C

A OR B AND C

A XOR B XOR C

A OR B OR C

50. Which type of device FPGA are?

SLD

PLD

SROM

EEPROM

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