Digital Electronics Quiz Vol- 2

This is the Digital electronics quiz vol- 2 which is more advanced than Digital Electronics Quiz-1. This is a bit more advanced version of it. Enjoy the Quiz game there will be 50 questions.

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1.  The D flip-flop has _______ input.


2. An S-R Flip-Flop has 2 inputs marked ______& ______ and two outputs __&__.


3. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?


4. In DOWN-counter, each flip-flop is triggered by _______


5. A register that is used to store binary information is called a ________.


6. If the number of states in a counter are 2n, then the value of ‘n’ is ______


7. lf,  A and B are the inputs of a half adder, the carry is given by


8. Total number of inputs in a half adder is _____


9. _____ input in an S-R Flip-Flop resets the flip-flop to its original value with an output Q, that will be at Logic ‘0’ or ‘1’ depending upon the set/reset condition.


10. A register can be defined as ______


11. Which flip flops serve to be the fundamental building blocks of counters?


12. How is a J-K flip-flop made to toggle?


13. On a master-slave flip-flop, when is the master enabled?


14. A PLA is similar to a ROM in concept except that ______


15. Why is the extent of propagation delay in synchronous counter much lesser than that of the asynchronous counter?



16. JK flip flop has _____


17. In which operation carry is obtained?


18. In D flip-flop, if clock input is LOW, the D input ______


19. _____ input in an S-R Flip-Flop resets the flip-flop to its original value with an output Q, that will be at Logic ‘0’ or ‘1’ depending upon the set/reset condition.


20. How many types of registers available?


21. The SR flip-flop can be considered as a ___ memory


22. Basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?


23. The register is a type of ________


24. In FPGA, vertical and horizontal directions are separated by __________


25. Define trigger pulse?


26. The inputs in the PLD is given through _______


27. The output of Up counters goes on increasing due to _____


28. A feature that distinguishes the J-K flip-flop from the D flip-flop is the


29. Schmitt trigger can be used as


30. The main difference between a register and a counter is ______


31. Why do the D flip-flops are said to be as Data Flip-flops’?


32. What amongst the following is faster in operation?


33. The process to activate a Flip-Flop is______


34. In SR flip-flop, ‘S’ stands for:


35. When the J and K inputs are low, the state of the outputs Q and Q’ are


36. UP-DOWN counter is a combination of _______


37. A counter circuit is usually made up of _____


38. A shift register is defined as ______


39. D flip-flop can be made from a J-K flip flop by making


40. In D flip-flop, if clock input is HIGH & D=1, then output is ______[quads id=1]




41. How many AND, OR and EXOR gates are required for the configuration of full adder?


42. In serial shifting method, data shifting occurs ______


43. In an UP-counter, each flip-flop is triggered by _______


44. In an S-R Flip-Flop, Q output is set to logic 1 by applying logic 0 to the _____.


45. If A, B, and C are the inputs of a full adder then the sum is given by ______


46. Which type of device FPGA are?


47. A modulus-10 counter must have _____


48. Which sequential circuits are used for counting pulses?


49. Three decade counter would have _______


50. Set pin going high in SR flip flop causes the output to go to


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